Be careful not to load the wrong file to a hardware!
| filename | comment |
|---|---|
| 20250702_1301_dirich5d2_any_in.bit | Design for DIRICH5D2 with hit input multiplexer to select between inputs from amplifiers or from addon connector JPIGGY1 (DOG_TDC_HIT_IN_SEL). Only lightly tested at the moment. |
| 20250701_1510_dirich5d2_piggy_lvdsin1.bit | Design for DIRICH5D2 with DIRICH5D_PIGGY_LVDSIN1 addon (addon with 2x KEL 40-pin connectors for connection of front-ends via 40-pol flat calbes, 16x LVDS in plus SPI interface). |
| 20250611_2021_dirich5d2_dep.bit | DIRICH5D2 design with improved diagnostics and and trigger/daq enable register (DOG_DAQ_CTRL[12]) so that trigger acceptance is disabled by default after reboot and needs to be actively enabled after event builder addresses have been configured. |
| 20250611_1309_dogma_hub1_dcm.bit | DOGMA_HUB1_DCM design with improved trigger rejected counter and global DCM trigger/DAQ enable/disable register (DCM_TRIG_ENABLE / 0x25). |
| 20250610_1018_dirich5d2_dep.bit | DIRICH5D2 design with improved diagnostics and and trigger/daq enable register (DOG_DAQ_CTRL[12]) so that trigger acceptance is disabled by default after reboot and needs to be actively enabled after event builder addresses have been configured. |
| 20250526_2258_dogma_hub1.bit | Design for a generic dogma hub (not the DCM!). This design is for additional hubs in the dogma network (nedded to increase the number of downlinks) and needs to be connected with its UL1 (uplink) port to a DLx (downlink) port of the DCM or to another hub that already has an uplink towards the DCM. |
| 20250415_2228_muppet1_dog_template.bit | Bitfile for MUPPET1_DOG_TEMPLATE design which just provides some registers for reading and writing with the dogma tools on the MUPPET1 module. |
| 20241211_0905_dogma_hub1_dcm.bit | HeH: Added external LVDS trigger inputs on add-on pin pairs ADF_PP0 and ADR_PP0. Trigger inputs need to be enabled using DCM_EXT_TRG_IN_EN register. |
| 20241028_0902_dirich5d2_dep.bit | Fixed GbE RX hangup under severe overload issue. Upgraded SPI master, now supporting all 4 SPI modes. |
| 20210526_dirich_thresholds.jed | Bitfile for the dirich satellite DAC FPGAs (threshold FPGAs). |